Researchers to redesign microprocessors to increase computing power

A man wearing glasses and a maroon sweater gestures toward a computer screen displaying information about microprocessors while he talks to someone off to the side of the camera.

Vijaykrishnan Narayanan, A. Robert Noll Chair of Electrical Engineering and Computer Science at Penn State, is leading the efforts to explore new methods of improving computing power in microprocessors.

Image: Penn State College of Engineering

Increasing computing power is critical for many technological developments. However, the traditional methods of increasing computing power – namely, adding more transistors to microprocessors – is reaching its limit of physical scaling. With a three-year, $500,000 grant from the National Science Foundation, researchers led by Vijaykrishnan Narayanan, A. Robert Noll Chair of Electrical Engineering and Computer Science at Penn State, are exploring new methods of improving computing power in microprocessors.

A microprocessor is a central processing unit made of transistors, the switches that change electrical signals. In order to improve computing power, scientists pack more transistors into a single microprocessor by making the transistors smaller. However, transistors are becoming as small as physically possible, according to Narayanan. To improve microprocessors and their computing power, scientists have to build the microprocessors differently – more specifically, they have to build up.

“There used to be only one layer of transistors because of fabrication challenges, but now we are looking at multiple layers of these transistors stacked upon each other,” Narayanan said. “Think about making a stack of pancakes. The pancakes can be made separately and stacked on top of each other, and that is what is being done now. But with the notion of microprocessor technology, when you stack things, it’s not enough that you stack; the stacks need to communicate with each other.”

In order to increase communication between the layers, which is important for the speed of processing, the layers cannot be premade and then stacked. Instead, they must be created as they are being layered. However, creating the layers as they are being stacked means that the top layers behave differently from the bottom layers, requiring new design strategies.

“We’re aware that the performance of the different layers is slightly different, so how do you make a more powerful processor with this?” Narayanan said. “What I’m looking at, within the boundaries of these limitations, is how well are we able to allocate the design to different layers. What needs to be at the top layer, if I move things there, how should I design them to enhance power, performance, robustness?”

The ultimate goal of the research, Narayan said, is to explore the types of opportunities that come into play when the microprocessors have another dimension that simultaneously allows for greater connectivity between the layers.

“When we can do these types of things, we’ll have the ability to integrate different technologies together as a single chip,” Narayanan said. “We can tightly integrate non-volatile memory that can retain data with logic, even if the power goes away. Think of turning on your phone and everything comes back instantly. With a lot of fine grain connectivity, we’ll be almost instantaneously backing up everything. The impact on high-performance processors would be significant as well.”

Narayanan will continue to leverage ongoing external collaborations with other researchers, including Suman Datta, Stinson Professor of Nanotechnology at the University of Notre Dame, and Meng-Fan Chang, professor at National Tsing Hua University in Taiwan. The new project grew out of work conducted with a grant from the Center for Research on Intelligent Storage and Processing-in-memory, of the Joint University Microelectronics Program in the Semiconductor Research Corporation.

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